融合數字電路與存內計算的高能效神經網絡處理器-英文版嶽金山 9787302656005 【台灣高等教育出版社】

Name: 融合數字電路與存內計算的高能效神經網絡處理器-英文版 嶽金山 9787302656005 【台灣高等教育出版社】
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書名：融合數字電路與存內計算的高能效神經網絡處理器-英文版
ISBN：9787302656005
出版社：清華大學
著編譯者：嶽金山
頁數：118
所在地：中國大陸 *此為代購商品
書號：1674970
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內容簡介

神經網路演算法在諸多領域具有廣泛應用，本書針對神經網路在低功耗智能設備上實際應用中遇到的關鍵挑戰，研究了融合數字電路與存內計算的高能效神經網路處理器。本書創新成果包括：?提出了一種基於特定卷積核的數據復用架構，提升了能量效率；?針對不規則稀疏的額外硬體開銷，設計了頻域神經網路處理器，支持高效FFT計算和頻域二維數據復用；?提出了一種存內計算系統架構，支持分塊結構化稀疏、數據復用與ADC動態關斷；?針對現有存內計算晶元難以支持大規模網路的挑戰，提出了組相聯稀疏存內計算架構，支持乒乓權重更新，並進行了流片驗證。本書展示了融合數字電路與存內計算的技術路線。證明充分利用數字電路與存內計算的優勢，結合器件、電路、架構和演算法應用等多層次聯合優化能夠實現更高能效。

1 Introduction
1 1 Research Background and Significance
1 1 1 Development Trends of Neural Network
1 1 2 Requirements of NN Processor
1 1 3 Energy-Efficient NN Processors
1 2 Summary of the Research Work
1 2 1 Overall Framework of the Research Work
1 2 2 Main Contributions of This Book
1 3 Overall Structure of This Book
References
2 Basics and Research Status of Neural Network Processors
2 1 Basics of Neural Network Algorithms
2 2 Basics of Neural Network Processors
2 3 Research Status of Digital-Circuits-Based NN Processors
2 3 1 Data Reuse
2 3 2 Low-Bit Quantization
2 3 3 NN Model Compression and Sparsity
2 3 4 Summary of Digital-Circuits-Based NN Processors
2 4 Research Status of CIM NN Processors
2 4 1 CIM Principle
2 4 2 CIM Devices
2 4 3 CIM Circuits
2 4 4 CIM Macro
2 4 5 Summary of CIM NN Processors
2 5 Summary of This Chapter
References
3 Energy-Efficient NN Processor by Optimizing Data Reuse for Specific Convolutional Kernels
3 1 Introduction
3 2 Previous Data Reuse Methods and the Constraints
3 3 The KOP3 Processor Optimized for Specific Convolutional Kernels
3 4 Processing Array Optimized for Specific Convolutional Kernels
3 5 Local Memory Cyclic Access Architecture and Scheduling Strategy
3 6 Module-Level Parallel Instruction Set and the Control Circuits
3 7 Experimental Results
3 8 Conclusion
References
4 Optimized Neural Network Processor Based on Frequency-Domain Compression Algorithm
4 1 Introduction
4 2 The Limitations of Irregular Sparse Optimization and CirCNN Frequency-Domain Compression Algorithm
4 3 Frequency-Domain NN Processor STICKER-T
4 4 Global-Parallel Bit-Serial FFT Circuits
4 5 Frequency-Domain 2D Data-Reuse MAC Array
4 6 Small-Area Low-Power Block-Wise TRAM
4 7 Chip Measurement Results and Comparison
4 8 Summary of This Chapter
References
5 Digital Circuits and CIM Integrated NN Processor
5 1 Introduction
5 2 The Advantage of CIM Over Pure Digital Circuits
5 3 Design Challenges for System-Level CIM Chips
5 4 Sparse CIM Processor STICKER-IM
5 5 Structural Block-Wise Weight Sparsity and Dynamic Activation Sparsity
5 6 Flexible Mapping and Scheduling and Intra/Inter-Macro Data Reuse
5 7 Energy-Efficient CIM Macro with Dynamic ADC Power-Off
5 8 Chip Measurement Results and Comparison
5 9 Summary of This Chapter
References
6 A 「Digital+CIM」 Processor Supporting Large-Scale NN Models
6 1 Introduction
6 2 The Challenges of System-Level CIM Chips to Support Large-Scale NN Models
6 3 「Digital+CIM」 NN Processor STICKER-IM
6 4 Set-Associate Block-Wise Sparse Zero-Skipping Circuits
6 5 Ping-Pong CIM and Weight Update Architecture
6 6 Ping-Pong CIM Macro with Dynamic ADC Precision
6 7 Chip Measurement Results and Comparison
6 8 Summary of This Chapter
References
7 Summary and Prospect
7 1 Summary of This Book
7 2 Prospect of This Book

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