計算機組成與設計-硬體軟件介面 RISC-V版 (英文版.原書第2版) 9787111742661 戴維.A.帕特森

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書名：計算機組成與設計-硬體/軟件介面 RISC-V版 (英文版.原書第2版)
ISBN：9787111742661
出版社：機械工業
著編譯者：戴維.A.帕特森約翰.L.亨尼斯
頁數：712
所在地：中國大陸 *此為代購商品
書號：1615547
可大量預訂，請先連絡。

【台灣高等教育出版社簡體書】計算機組成與設計-硬體/軟件介面 RISC-V版 (英文版.原書第2版) 787111742661 戴維.A.帕特森約翰.L.亨尼斯

內容簡介

本書由2017年圖靈獎得主Patterson和Hennessy共同撰寫，是計算機體繫結構領域的經典書籍，強調軟硬體協同設計及其對性能的影響。本書採用開源的RISC-V指令系統體繫結構，講解硬體技術、指令、算術運算、流水線、存儲層次、I/O以及并行處理器等。第2版將RV64切換為RV32以降低學習難度，新增關於領域定製體繫結構（DSA）的討論以反映新的技術趨勢。此外，每一章都增加了「性能提升」和「自學」章節，並更新了大量練習題。本書適合計算機體繫結構領域的專業技術人員參考，也適合高等院校計算機相關專業的學生閱讀。

作者簡介

約翰·L 亨尼斯（John L Hennessy），Hennessy與Patterson共同榮獲了2017年度圖靈獎以及2022年度查爾斯·斯塔克·德拉普爾獎。Hennessv是斯坦福大學第十任校長，現為Google母公司AIphabet的非執行董事長，斯坦福大學Knight—Hennessy學者獎學金項目主管。他是IEEE和ACM會士。美國國家工程院、美國國家科學院、美國哲學院以及美國藝術與科學院院士。他於1981年開始研究MIPS項目，之後創辦MIPS Computer Systems公司。開發了最早的商用RISC微處理器之一。他還領導了DASH項目，設計了第一個可擴展cache一致性多處理器原型。

1 Computer Abstractions and Technology
1 1 Introduction
1 2 Seven Great Ideas in Computer Architecture
1 3 Below Your Program
1 4 Under the Covers
1 5 Technologies for Building Processors and Memory
1 6 Performance
1 7 The Power Wall
1 8 The Sea Change: The Switch from Uniprocessors to Multiprocessors
1 9 Real Stuff: Benchmarking the Intel Core i
1 10 Going Faster: Matrix Multiply in Python
1 11 Fallacies and Pitfalls
1 12 Concluding Remarks
1 13 Historical Perspective and Further Reading
1 14 Self-Study
1 15 Exercises
2 Instructions: Language of the Computer
2 1 Introduction
2 2 Operations of the Computer Hardware
2 3 Operands of the Computer Hardware
2 4 Signed and Unsigned Numbers
2 5 Representing Instructions in the Computer
2 6 Logical Operations
2 7 Instructions for Making Decisions
2 8 Supporting Procedures in Computer Hardware
2 9 Communicating with People
2 10 RISC-V Addressing for Wide Immediates and Addresses
2 11 Parallelism and Instructions: Synchronization
2 12 Translating and Starting a Program
2 13 A C Sort Example to Put it All Together
2 14 Arrays versus Pointers
2 15 Advanced Material: Compiling C and Interpreting Java
2 16 Real Stuff: MIPS Instructions
2 17 Real Stuff: ARMv7 (32-bit) Instructions
2 18 Real Stuff: ARMv8 (64-bit) Instructions
2 19 Real Stuff: x86 Instructions
2 20 Real Stuff: The Rest of the RISC-V Instruction Set
2 21 Going Faster: Matrix Multiply in C
2 22 Fallacies and Pitfalls
2 23 Concluding Remarks
2 24 Historical Perspective and Further Reading
2 25 Self-Study
2 26 Exercises
3 Arithmetic for Computers
3 1 Introduction
3 2 Addition and Subtraction
3 3 Multiplication
3 4 Division
3 5 Floating Point
3 6 Parallelism and Computer Arithmetic: Subword Parallelism
3 7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x
3 8 Going Faster: Subword Parallelism and Matrix Multiply
3 9 Fallacies and Pitfalls
3 10 Concluding Remarks
3 11 Historical Perspective and Further Reading
3 12 Self-Study
3 13 Exercises
4 The Processor
4 1 Introduction
4 2 Logic Design Conventions
4 3 Building a Datapath
4 4 A Simple Implementation Scheme
4 5 Multicycle Implementation
4 6 An Overview of Pipelining
4 7 Pipelined Datapath and Control
4 8 Data Hazards: Forwarding versus Stalling
4 9 Control Hazards
4 10 Exceptions
4 11 Parallelism via Instructions
4 12 Putting It All Together: The Intel Core i7 6700 and ARM Cortex
4 13 Going Faster: Instruction-Level Parallelism and Matrix Multiply
4 14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and
More Pipelining Illustrations
4 15 Fallacies and Pitfalls
4 16 Concluding Remarks
4 17 Historical Perspective and Further Reading
4 18 Self-Study
4 19 Exercises
5 Large and Fast: Exploiting Memory Hierarchy
5 1 Introduction
5 2 Memory Technologies
5 3 The Basics of Caches
5 4 Measuring and Improving Cache Performance
5 5 Dependable Memory Hierarchy
5 6 Virtual Machines
5 7 Virtual Memory
5 8 A Common Framework for Memory Hierarchy
5 9 Using a Finite-State Machine to Control a Simple Cache
5 10 Parallelism and Memory Hierarchy: Cache Coherence
5 11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
5 12 Advanced Material: Implementing Cache Controllers
5 13 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Memory Hierarchies
5 14 Real Stuff: The Rest of the RISC-V System and Special Instructions
5 15 Going Faster: Cache Blocking and Matrix Multiply
5 16 Fallacies and Pitfalls
5 17 Concluding Remarks
5 18 Historical Perspective and Further Reading
5 19 Self-Study
5 20 Exercises
6 Parallel Process
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